The present invention relates to low-power systems and subsystems employing microprocessors, and to integrated circuit elements which help to manage the low-level operation of a microprocessor.
The very rapid progress of integrated circuit complexity generally, and the general use of CMOS processing, have permitted a huge increase in the functionality which can be included in a very compact portable system. The availability of low-power LCD displays has further speeded the advance of such systems. However, power supply capabilities have not advanced as rapidly. Battery technology has provided a relatively slow increase in the amount of energy which can be stored per unit weight (or per unit volume). Thus, in order to provide complex functionality in a small portable module, a very high degree of power efficiency has become an enabling technology.
A separate line of technological progress is the increasing use of batteries, in integrated circuit packages or in very small modules, to provide nonvolatile data retention. Here the driving concern is not the system power budget, but reliability and robustness. The availability of battery backup can be used to ensure that power outages or power-line noise cannot cause loss of data (including configuration data). For example, modern semiconductor technology has provided solid-state memories with such low standby power requirements that a single coin-sized battery can power the memory for ten years of lifetime or more. Such memories are already commercially available.
Low-power microcontrollers have also been commercially available in recent years. An unusual example of such a microcontroller is the DS5000 Soft MicroController.TM.. (This integrated circuit and its data sheet are available from Dallas Semiconductor Corporation, 4350 Beltwood Parkway, Dallas, Tex. 75244, and are both hereby incorporated by reference.) The DS5000 is a microcontroller which has a small battery packaged with it, to provide nonvolatility. Microprocessors and microcontrollers of this kind are extremely useful, since the internal memory of the microprocessor is always preserved. Therefore, the microprocessor can be programmed to "learn" while in service, or to internally store a parameter set which is adjustable throughout the lifetime of the microprocessor. However, aside from their nonvolatility, such microprocessors are typically not the highest-performing microprocessors. Thus, a user who needs nonvolatility may need to make some difficult choices.
The present invention provides an auxiliary integrated circuit, which can interface with a microprocessor (or other complex random logic chip) in a way which improves the microprocessor's power management during power-up and power-down transitions.
In the presently preferred embodiment, this auxiliary chip provides all necessary functions for power supply monitoring, reset control, and memory back-up in microprocessor based systems. A precise internal voltage reference and comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the microprocessor reset and power fail outputs are forced active, and static RAM control unconditionally write protects external memory. The auxiliary chip also provides early warning detection by driving a non-maskable interrupt at a user defined voltage threshold. External reset control is provided by a pushbutton reset input which is debounced and activates reset outputs. An internal timer also forces the reset outputs to the active state if the strobe input is not driven low prior to time out. Reset control and wake-up/sleep control inputs also provide necessary signals for orderly shut down and start up in battery backup and battery operate applications.
The auxiliary chip provided by the present invention can be used with a very wide variety of different microcontrollers and microprocessors. Two significantly different types must be distinguished:
For low-power battery-backed CMOS microcontrollers and microprocessors (such as the DS5000), the microprocessor should not be reset when power is failing (because such a reset will wake up the microprocessor, and cause it to draw power).
For NMOS microprocessors, and for CMOS microprocessors or microcontrollers which do not have access to a backup power supply, it is desirable to reset the processor as soon as possible when the power supply is failing, and keep it in reset until the power supply begins to recover. (Bringing the microprocessor under control early helps minimize power consumption, and helps to avoid random outputs from the microprocessor.)
A battery-backed microprocessor should preferably go into its "stop" mode when power goes down. However, the microprocessor alone does not normally know when it has been switched over to battery backup.
Another of the innovative teachings set forth in the present application is an auxiliary chip which sends a reset command to an associated microprocessor at a certain voltage level, but only if the direction of voltage change indicates that the power supply is coming up, and not going down. This permits the microprocessor to be reset, and resume operation, as early as possible when power is restored, but prevents a nonvolatized microprocessor from being reset during its low-power state.
Another of the innovative teachings set forth in the present application is that the microprocessor can access the auxiliary chip to ascertain the power history. That is, the microprocessor can direct an interrupt to the auxiliary chip, which will cause the auxiliary chip to respond with a signal which indicates to the microprocessor whether the power supply voltage is heading up or down. When the microprocessor is reset at power-up, and detects that the power supply voltage is still marginal, the present invention permits the microprocessor to determine (by querying the auxiliary chip) whether the supply voltage is marginal, so that the microprocessor does not go into full operation until the supply voltage is high enough.
Another of the innovative teachings set forth in the present application is a control relationship which permits the auxiliary chip itself to be put to sleep by the microprocessor to minimize power consumption. The sleep mode of the auxiliary chip saves power by shutting down many of the input-sensing circuits. (The sleep mode also gives users a way to turn off the watchdog functions of the auxiliary chip.) To minimize the risk of the system getting stuck with the auxiliary chip in sleep mode, and the risk of electrical noise on the microprocessor outputs (which normally occurs during reset) from throwing the auxiliary chip into sleep mode, the present invention imposes a timing relationship where the sleep command is not accepted unless it stands in the proper timing relationship to a signal on the strobe pin. This permits the power savings of the sleep mode to be realized, without any risk of the system being placed in the sleep mode due to an out-of-control system condition.
This auxiliary chip, and systems or subsystems which use this auxiliary chip, provide at least the following advantages:
- Holds microprocessor in check during power transients;
- Halts and restarts an out-of-control microprocessor;
- Monitors pushbutton for external override;
- Warns microprocessor of an impending power failure;
- Converts CMOS SRAM into nonvolatile memory;
- Unconditionally write protects memory when power supply is out of tolerance;
- Consumes less than 100 nA of battery current;
- Can control an external power switch for high current applications;
- Provides orderly shutdown in nonvolatile microprocessor applications;
- Supplies necessary control for low power "stop mode" in battery operate hand held applications.
A further advantage of this auxiliary chip is that it provides designers with a greatly increased range of options. This auxiliary chip permits system designers to obtain many of the advantages of a specialized low-power microprocessor (such as the DS5000), while using a different microprocessor which has higher-speed, or more versatility, or compatibility with some existing software base, or special adaptation for some special purpose.
Thus, systems which include the combination of an auxiliary chip as described with a general-purpose microprocessor can have advantages including robustness in the face of power-supply crashes or glitches, and program resumption which appears (to the user) to be continuous with the program's operation at the moment when the machine was turned off (depending on how state-save operations are interwoven with software execution).
Normally, when it is desired to put a microprocessor into a known state, this is done by activating a reset. Some microprocessor architectures have reset lines running to every gate on the chip, so that a reset command will instantly reset every logical element to the known state. However, some architectures do not. For example, in the Intel 8051 architecture, several cycles are necessary after the reset command, to clock all of the logical elements on the chip into the known state. (This architecture is used not only in Intel's 80C51 microprocessor, but also in any other microprocessor which is to be compatible with this widely-used architecture.) For example, a simple example of a logic block which would require multiple cycles to reset would be a shift register, with a reset only at the input of the shift register. In this (hypothetical) case, it can be seen that, even after the reset command has provided a known state in the first stage of the shift register, unknown data may still exist in the following stages. Therefore, a series of clock commands must be provided, to propagate the known state all the way through the shift register.
Alternatively, if it is necessary to save the state of a microprocessor entering power-down, this can be done separately. For example, a "shadow" memory or register can be used to track the status of various on-chip registers, etc. Similarly, if desired, portions of on-chip memory can even be used as "shadow" scratch pad, to preserve some state information during such power-down operations.